1. Field of the Invention
The present invention relates to a priority detecting counter device for counting the number of "0's" or "1's" arranged from the most significant or the least significant of a binary number.
2. Description of the Background Art
In the numerical computation mainly including the scientific and technical computation, various computations with floating points are executed to increase the precision of the computations. The floating point add is one of the most frequently executed ones. Accordingly, when an attempt is made to speed up the numerical computing system using the floating point add, it is required to speed up the add.
In the add with the floating points, so-called "digit-down" occurs when signs of two operands are opposite and the values are close. Now, consider the sum of A=1.00000101.times.2.sup.111 and B=-1.11111101.times.2.sup.110 as an example. It is assumed that the mantissas and the exponents of the operands are represented by nine digits and three digits both in the binary notation, respectively. Accordingly, in order to do the coincidence of the digits of the exponents, a transformation to A=10.0000101.times.2.sup.110 is done, so that the add becomes as follows. A+B=(10.0000101-1.11111101).times.2.sup.110 =0.00001101.times.2.sup.110. Like in this example, zeros may stand in the head as a result of the add, which is called "digit-down". In this case, the number of zeros standing in the head is counted, on the basis of which the mantissa is shifted to the left and the value is subtracted from the exponent. That is to say, as five 0's stand including the unit in the head in this example, the mantissa is sifted by five digits to the left and 5 (represented as 101 in the binary notation) is subtracted from the exponent part, and then the result of the add is 1.10100000.times.2.sup.001. Accordingly, a priority detecting counter is required to count the number of zeros standing from the head of the bit string.
FIG. 8 shows the circuit configuration of the conventional art for performing the counting. It is shown in U.S. Pat. No. 4,785,421 "NORMALIZING CIRCUIT". In the figure, the reference numeral 51P denotes a register which stores mantissa computation result data D15-D0, 52 denotes a head "1" detection circuit for detecting the first "1" from the high order in the computation result data D15-D0, 53 denotes an encoder for coding and outputting the number of "0's" standing in the head from the values of the outputs S15-S0 of the detection circuit 52, 54P denotes a shifter for sifting the computation result data D15-D0 on the basis of an output 56P (5-bit data) coded by the encoder 53, and 55P denotes an adder for subtracting the output 56P of the encoder 53 from data 57 which provides a value of the exponent part. In this example, the bit length of the data is assumed to be 16 bits, the outputs of the register 51P are represented by D15-D0 in order from the high order side and the outputs of the head "1" detection circuit 52 are represented by S15-S0 in order from the high order side.
The structure of the head "1" detection circuit 52 is shown in FIG. 9. This detection circuit 52 is composed of sixteen blocks in total which are represented by A15-A0, respectively. The block A15 includes an AND circuit 61, n-channel MOS transistors 62 and 63 and an inverter circuit 64, and other blocks A14-A1 have the same structure as that of the block A15. The n-channel MOS transistor 62 forms a transmission gate. The block A0 includes only an AND circuit 65. The operation of this circuit 52 is described in the fifth column line 32 to the sixth column line 26 in the U.S. Pat. No. 4,785,421 mentioned above, and so the description thereof is not repeated herein. With this structure, only one of the outputs S15-S0 which corresponds to an input bit which attains "1" first from the high order side attains "1", and other outputs all go "0".
Subsequently, the encoder 53 of FIG. 8 generates the 5-bit binary data 56P indicating the number of "0's" in the head, from the one of the signals S15-S0 which attains "1" first from the high order side.
The conventional "0" counting circuit having such structure as described above has a problem of low operation speed. That is to say, in the head "1" detection circuit 52 shown in FIG. 8, fifteen transmission gates 62 in total are connected in series as shown in FIG. 9 and therefore the delay in signal transmission from input of the signal D15 to output of the signal S0 is determined by a processing time of seventeen stages in all, i.e., one stage of inverter (64), fifteen stages of transmission gates and one stage of AND circuit, in the worst case. Especially, connecting a large number of transmission gates in series causes considerable deterioration in speed. Accordingly, it can be said that the conventional structure is not suitable for the high-speed operation.
Furthermore, in the conventional structure, it must further pass through the encoder (53) to count the number of headmost "zeros", so that the delay time further increases. Moreover, if the bit length of the operands increases, then the number of stages of the circuit increases in proportion to it, so that it can also be said that the conventional structure is not suitable for processing of a large number of bits.